Advanced PCB Layout – Step by Step

Advanced PCB Layout – Step by Step

by Robert Feranec , Shared by: Erin KOU

Here summarized these steps, which will guide you during PCB Layout process. Let me know when you find them useful.

First Phase – Connecting all the pins

Step 1:	Set up basic rules For example [mm]: Track 0.1 / 0.1 (clearance / width) , VIA 0.45/0.2 (diameter / drill), DIFF pair 0.1/0.1/0.1 (track / gap / track)
Step 2:	Set up a basic stackup Add more layers and you will remove unused layers on the end.
Step 3:	Do preliminary memory layout Connect all the memory pins. Leave space for length matching.
Step 4:	Do CPU fanouts By priority (first with highest priority): Powers, Decoupling capacitors, Precise resistors / capacitors, Crystals, Series resistors / capacitors, Termination resistors, Pull UP / DOWN resistors, Bootstrap resistors.
Step 5:	Do fanout for other difficult BGAs in design (e.g. FPGA, chipset, …)
Step 6:	Route big and wide buses (e.g. PCI, ISA, …) Do all the fanouts in the way of the bus, so you don’t have to reroute it later.
Step 7:	Do preliminary differential pair routing
Step 8:	Connect Long Length Buses, then rest of High pin number buses
Step 9:	Do local connectionsThese are usually connections in small area e.g. Power supply components, Small circuits, Connectors, Analog areas
Step 10:	Connect rest of the still unconnected signals (e.g. 1 wire nets, LEDs, …)
Step 11:	(or Step 0) Connect power netsDesign power planes. If your design is difficult, or number of power layers is very limited, you may want to do preliminary power distribution on very beginning of layout.
Step 12:	Clear DRCs

Second Phase – Improving your Layout

Step 1:	Set the real stackupUse the information provided by your PCB manufacturer or design your own.
Step 2:	Set the real differential pair rules based on stackupUse the track geometry provided by your PCB manufacturer
Step 3:	Do preliminary memory interface length matchingThe signals don’t have to be nice at this stage, the goal is occupy the space needed to length match the signals.
Step 4:	Do preliminary differential pair length matchingReroute differential pairs with the new track geometry defined by target impedance & stackup, occupy the space needed to length match the signals later.
Step 5:	Add stitching VIAsFind more information for example here (page 11).
Step 6:	Do preliminary length matching of other signals (e.g. clocks, …)
Step 7:	Check high current tracks Add / modify polygons were needed. Calculate track width and VIA number.
Step 8:	Check power planes Go from the source, be sure there is enough vias and copper for the current.
Step 9:	Check all the nets one-by-one Go through all the nets in your board. Double check for example wider space around clock signals, interrupts, …
Step 10:	Do final length matching of simple signals & differential pairs
Step 11:	Do final length matching of memory interface
Step 12:	Lock down important tracks (e.g. memory interface tracks)
Step 13:	Add: Company name, Copyright, Year, Board name & Version, …
Step 14:	Add manufacturing information (e.g. PCB color, Tolerances,  …)

website: www.pcbway.com/e

For PCB prototype, please feel easy contact Erin KOU (erin.kou@pcbway.com)